View MK3722_230326.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MK3722
VCXO PLUS AUDIO CLOCK FOR STB
Description
The MK3722 is a low cost, low jitter, high performance VCXO and PLL clock synthesizer designed to replace expensive discrete VCXOs and multipliers. The patented on-chip Voltage Controlled Crystal Oscillator accepts a 0 to 3.3 V input voltage to cause the output clocks to vary by 115 ppm. Using ICS' analog/digital Phase-Locked Loop (PLL) techniques, the device uses an inexpensive 27 MHz pullable crystal input to produce a reference output and a selectable audio clock. ICS manufactures the largest variety of VCXO based timing devices for all applications. Consult ICS to eliminate VCXOs, crystals, and oscillators from your board. The frequency of the on-chip VCXO is adjusted by an external control voltage connected to VIN. Because VIN is a high impedance input, it can be driven directly from an PWM RC integrator circuit.
Features
* * * * * *
Packaged in 16 pin TSSOP Replaces a VCXO and oscillator Operating voltage of 3.3V Provides output of 27 MHz plus audio clock Uses an inexpensive 27 MHz pullable crystal On-chip patented VCXO with pull range of 230 ppm (minimum)
* VCXO tuning voltage of 0 to 3.3 V * Advanced, low power, sub-micron CMOS process
Block Diagram
VDD
3
S2:S0 VIN X1 27 MHz Pullable Crystal
3
PLL/Clock Synthesis Circuitry
ACLK
X2
Voltage Controlled Crystal Oscillator
3
27MHz
GND
PDTS
MDS 3722 B In tegr ated C ir cu it S yst ems
q
1
5 25 Ra ce Str eet, San Jose, C A 95 126
q
Revision 092502 tel ( 408) 2 95-9 800
q
www. i c s t. c om
MK3722 VCXO PLUS AUDIO CLOCK FOR STB
Pin Assignment
X2 X1 VD D VD D VIN GND GND PD TS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 S1 NC VDD S0 27M GND AC LK S2
Audio Clock Select Table
S2
0 0 0 0 1 1 1 1
S1
0 0 1 1 0 0 1 1
S0
0 1 0 1 0 1 0 1
ACLK (MHz)
8.192 11.2896 12.288 16.9344 18.432 16.384 22.5792 24.576
16 Pin 4.40m m body, 0.65m m pitch TSSO P
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Pin Name
X2 X1 VDD VDD VIN GND GND PDTS S2 ACLK GND 27M S0 VDD NC S1
Pin Type
Output Input Power Power Input Power Power Power Input Output Power Output Input Power -Input
Pin Description
Crystal connection. Connect to a 27MHz fundamental mode pullable crystal. Crystal connection. Connect to a 27MHz fundamental mode pullable crystal. Connect to +3.3 V. Connect to +3.3 V. Voltage input to VCXO. Zero to 3.3V signal which controls the VCXO frequency. Connect to ground. Connect to ground. Power Down Tri-state. This pin powers down entire chip and tri-states the outputs when low. Internal pull-up. Select input S2. Selects ACLK per table above. Internal pull-up. Audio clock output per table above. Connect to ground. 27MHz reference clock output. Select input S0. Selects ACLK per table above. Internal pull-up. Connect to +3.3V. No connect. Do not connect anything to this pin. Select input S1. Selects ACLK per table above. Internal pull-up.
MDS 3722 B Int egrat ed C ircuit Syste ms
q
2
525 R ace S tr eet, San Jose, CA 95126
q
Revision 092502 t el (40 8) 295 -9800
q
w ww. ic s t .c o m
MK3722 VCXO PLUS AUDIO CLOCK FOR STB
External Component Selection
The MK3722 requires a minimum number of external components for proper operation.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed capacitors, one between X1 and ground, and another between X2 and ground. Stuffing of these capacitors on the PCB is optional. The need for these capacitors is determined at system prototype evaluation, and is influenced by the particular crystal used (manufacture and frequency) and by PCB layout. The typical required capacitor value is 1 to 4 pF. To determine the need for and value of the crystal adjustment capacitors, you will need a PC board of your final layout, a frequency counter capable of about 1 ppm resolution and accuracy, two power supplies, and samples of the crystals which you plan to use in production. You will also need measured initial accuracy for each crystal at the specified crystal load capacitance (CL). To determine the value of the crystal capacitors: 1. Connect VDD to 3.3V. Connect pin 5 to the second power supply. Adjust the voltage on pin 5 to 0V. Measure and record the frequency of the CLK output. 2. Adjust the voltage on pin 5 to 3.3V. Measure and record the frequency of the same output. To calculate the centering error:
6 ( f 3.3 ( 3.0 )V - f t arg et ) + ( f 0V - f t arg et ) Error = 10 x --------------------------------------------------------------------------------------- - errorxtal f t arg et
Decoupling Capacitors
Decoupling capacitors of 0.01F should be connected between VDD and GND on pins 3 and 4, pins 6 and 7, and pins 11 and 14 as close to the MK3722 as possible. For optimum device performance, the decoupling capacitors should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB traces between the clock outputs and the loads are over 1 inch, series termination should be used. To series terminate a 50 trace (a commonly used trace impedance) place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20.
Quartz Crystal
The MK3722 VCXO function consists of the external crystal and the integrated VCXO oscillator circuit. To assure the best system performance (frequency pull range) and reliability, a crystal device meeting ICS' recommended parameters must be used, and the layout guidelines discussed in the following section must be followed. See Application Note MAN05 for a full list of crystal parameters. The frequency of oscillation of a quartz crystal is determined by its "cut" and by the load capacitors connected to it. The MK3722 incorporates on-chip variable load capacitors that "pull" (change) the frequency of the crystal. The crystal specified for use with the MK3722 is designed to have zero frequency error when the total of on-chip + stray capacitance is 14pF. The external crystal must be connected as close to the chip as possible and should be on the same side of the PCB as the MK3722. There should be no via's between the crystal pins and the X1 and X2 device pins. There should be no signal traces underneath or close to the crystal.
Where: ftarget = nominal crystal frequency errorxtal =actual initial accuracy (in ppm) of the crystal being measured If the centering error is less than 25 ppm, no adjustment is needed. If the centering error is more than 25ppm negative, the PC board has excessive stray capacitance and a new PCB layout should be considered to reduce stray capacitance. (Alternately, the crystal may be re-specified to a higher load capacitance. Contact ICS for details.) If the centering error is more than 25ppm positive, add identical fixed centering capacitors from each crystal pin to ground. The value for each of these caps (in pF) is given by:
MDS 3722 B Int egrat ed C ircuit Syste ms
q
3
525 R ace S tr eet, San Jose, CA 95126
q
Revision 092502 t el (40 8) 295 -9800
q
w ww. ic s t .c o m
MK3722 VCXO PLUS AUDIO CLOCK FOR STB
External Capacitor = 2 x (centering error)/(trim sensitivity) Trim sensitivity is a parameter which can be supplied by your crystal vendor. If you do not know the value,
assume it is 30 ppm/pF. After any changes, repeat the measurement to verify that the remaining error is acceptably low (typically less than 25ppm).
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK3722. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Soldering Temperature 7V
Rating
-0.5V to VDD+0.5V 0 to +70C -65 to +150C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Reference crystal parameters
Min.
0 +3.15
Typ.
Max.
+70 +3.45
Units
C V
Refer to page 3
DC Electrical Characteristics
VDD=3.3V 5% , Ambient temperature 0 to +70C, unless stated otherwise
Parameter
Operating Voltage Output High Voltage Output Low Voltage Output High Voltage (CMOS Level) Input High Voltage (S1:S0) Input High Voltage (S2) Input Low Voltage (S1:S0) Input Low Voltage (S2)
Symbol
VDD VOH VOL VOH VIH VIH VIL VIL
Conditions
IOH = -12 mA IOL = 12 mA IOH = -4 mA
Min.
3.15 2.4
Typ.
Max.
3.45 0.4
Units
V V V V V V
VDD-0.4 2.0 2.5 0.8 0.5
V V
MDS 3722 B Int egrat ed C ircuit Syste ms
q
4
525 R ace S tr eet, San Jose, CA 95126
q
Revision 092502 t el (40 8) 295 -9800
q
w ww. ic s t .c o m
MK3722 VCXO PLUS AUDIO CLOCK FOR STB
Parameter
Operating Supply Current Short Circuit Current VIN, VCXO Control Voltage On Chip Pull-up Resistor, inputs Input Capacitance Nominal Output Impedance
Symbol
IDD IOS VIA RPU CIN ZOUT
Conditions
No load, 2 outputs
Min.
Typ.
11 50
Max.
Units
mA mA
0 S0, S1, S2 S0, S1, S2 150 5 20
3.3
V k pF
AC Electrical Characteristics
VDD = 3.3V 5%, Ambient Temperature 0 to +70 C, unless stated otherwise
Parameter
Crystal Pullability VCXO Gain Output Rise Time Output Fall Time Output Clock Duty Cycle Maximum Output Jitter, short term tOR tOF tD tJ
Symbol
fP
Conditions
0V< VIN < 3.3V, Note 1 VIN = VDD/2 + 1V, Note 1 0.8 to 2.0V, CL=15pF 2.0 to 0.8V, CL=15pF Measured at 1.65V, CL=15pF CL=15pF
Min.
+ 100
Typ.
80 0.75 0.75
Max. Units
ppm ppm/V 1.5 1.5 60 ns ns % ps
40
50 +150
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
78 70 68 37
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
MDS 3722 B Int egrat ed C ircuit Syste ms
q
5
525 R ace S tr eet, San Jose, CA 95126
q
Revision 092502 t el (40 8) 295 -9800
q
w ww. ic s t .c o m
MK3722 VCXO PLUS AUDIO CLOCK FOR STB
Package Outline and Package Dimensions (16 pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95
16
Millimeters Symbol Min Max
Inches Min Max
E1 INDEX AREA
E
12 D
A A1 A2 b C D E E1 e L
-1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8
-0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8
A 2 A 1
A
c
-Ce
b SEATING PLANE
.10 (.004)
L
C
Ordering Information
Part / Order Number
MK3722G MK3722GTR
Marking
MK3722G MK3722G
Shipping packaging
Tubes Tape and Reel
Package
16 pin TSSOP 16 pin TSSOP
Temperature
0 to +70 C 0 to +70 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 3722 B Int egrat ed C ircuit Syste ms
q
6
525 R ace S tr eet, San Jose, CA 95126
q
Revision 092502 t el (40 8) 295 -9800
q
w ww. ic s t .c o m

▲Up To Search▲

Price & Availability of MK3722

	To Download MK3722 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .